This application relies for priority upon Korean Patent Application No. 2000-75643, filed on Dec. 12, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to method of forming semiconductor devices and, more particularly, to method of forming gate electrode of MOS transistor made of polycrystalline silicon-germanium and method of forming CMOS transistor device using the same.
PMOS transistors can be used having no relation to NMOS transistor in a semiconductor device. But, usually, PMOS transistors are used with NMOS transistor in CMOS type semiconductor devices. In a CMOS type semiconductor device, PMOS transistors and NMOS transistors are connected with each other and work together complementarily. Resultantly, the operation speed and efficiency of device can be improved and CMOS transistor has characteristics similar to those of bipolar type transistor. Therefore, the CMOS type semiconductor device is mainly used in high speed and quality devices.
As the size of elements becomes smaller to increase the integration level and operation speed and to improve voltage characteristic, dual gate type CMOS type devices are more frequently used among the CMOS type devices. In dual gate type devices, polycrystalline silicon forming gate electrode is doped with an impurity same as the source/drain region.
In the process of fabricating a high quality dual gate type CMOS transistor, as an impurity of gate electrode in PMOS transistor, Boron is generally used. And when ion implantation for source/drain region of PMOS transistor is executed, P type impurities such as Boron are also implanted into the polycrystalline silicon gate electrode.
However, Boron may cause gate depletion. The gate depletion means that the decrease in effective concentration of boron in polycrystalline gate electrode caused when the boron doping or activation of doped boron is not enough or when boron elements are diffused to gate insulation layer or to channel region beyond the gate. The diffused boron elements in channel or in gate insulation layer deteriorate the character of channel and gate insulation layer. And, the gate depletion lowers conductivity of gate and increases the effective thickness of gate insulation layer causing problems such as decrease in drain current.
Thus, when boron is used as an impurity of polycrystalline silicon gate, a method of preventing the gate depletion is needed. As the preventing method, a method of doping germanium to polycrystalline silicon gate electrode is well known to those who are skilled in the art. If germanium elements are added to polycrystalline silicon, solubility of the polycrystalline silicon to boron is increased to reduce an amount of diffused boron beyond the gate electrode through an annealing step.
FIG. 1 is a graph showing the change of resistance of polycrystalline silicon gate according to the change of concentration of germanium therein and the change of the amount of boron dose implanted therein. The measure of the resistance is made after the substrate is annealed for 30 seconds at the temperature of 600 Celsius degree. According to FIG. 1, at the same degree of boron dose, the resistance of polycrystalline silicon gate decreases as the concentration of germanium in polycrystalline silicon gate increase. And, at the same degree of boron dose, it is known that as the germanium concentration increases, the capacitance of gate also increases. (Investigation of Poly SiGe for dual gate CMOS technology, Wen-Chin Lee et. al., IEEE Electronic Device Letters, vol. 19, No. 7, July 1998)
A common method of doping germanium to gate electrode made of polycrystalline silicon is to supply germanium-contained gas as one of source gases in the process of depositing polycrystalline silicon layer. One more common method of doping germanium is to implant germanium into polycrystalline silicon layer ready made.
In case of supplying the germanium-contained gas, generally, GeH4 gas mixed with silane gas (SiH4) is supplied to the CVD process chamber during some time in the process of forming gate layer and thus silicon-germanium layer in the gate layer is made by in-situ type procedure. In this case, silicon germanium layer which contains 20xcx9c30 weight % of germanium and has better solubility compared with pure polycrystalline silicon can easily be acquired. But, in this method, controlling the process is so difficult that it is hard to secure uniformity and reliability of germanium concentration. Especially, for CMOS devices, as the CVD process is performed at high temperature that photoresist masking is unusable, the silicon germanium layer should be formed in the gate electrode of NMOS transistor as well as in the gate electrode of PMOS transistor. However, germanium, for example, germanium of 10% or more in the gate electrode of NMOS transistor lowers the solubility of polycrystalline silicon gate to N type impurities and lowers the capacitance of gate. This causes the degradation of transistor in CMOS devices.
In case of ion implantation method, by forming pure polycrystalline silicon gate layer and by forming photoresist pattern which covers NMOS region, boron ion (BF2+ or B+) can be doped only to polycrystalline silicon layer of PMOS transistor region. But, to obtain germanium of 20xcx9c30 weight % in polycrystalline silicon germanium gate, an amount of 1E16 ions/square centimeter or more dose corresponding to ion implantation continued for 10 or more hours are needed, which means the process does not have actual productivity.
Thus, a method of doping such a degree of germanium ion dose in a short duration, for example 1 hour, with exactness is needed.
It is therefore one feature of the present invention to solve the above mentioned problem of prior method of doping germanium in polycrystalline silicon gate layer.
Thus, it is an object of the present invention to provide a method of forming polycrystalline silicon germanium gate electrode by which a considerable amount of germanium can be doped effectively and to provide a method of forming CMOS transistor by using the same.
It is another object of the present invention to provide a method of forming polycrystalline silicon germanium gate electrode by which the doping concentration of germanium can be controlled with exactness and to provide a method of forming CMOS transistor by using the same.
It is also one object of the present invention to provide a method of forming CMOS transistor by which boron concentration can be sustained enough only in polycrystalline silicon gate electrode of PMOS transistor region.
For those purpose, the present invention propose a method of forming polycrystalline silicon germanium gate electrode including the steps of forming a gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer.
Generally, a step of boron doping to the polycrystalline silicon is made after the step of plasma doping of germanium. Here, the boron doping can be made by ion implantation or by the method of plasma doping.
In the present invention, the process of plasma doping of germanium may have the following steps: making a germanium containing plasma by supplying germanium source to a process chamber which has plasma enhancing devices, enhancing bias electric potential to the substrate for the formed germanium plasma to be accelerated to the substrate and to be injected into the substrate, more strictly to polycrystalline silicon layer revealed.
As a germanium source, GeH4, germanium halide like GeF4, solid germanium can be used. The concentration of germanium in the gate layer can be controlled by the amount and concentration of supplied germanium source gas and by controlling the time duration of the gas supply. The energy of germanium plasma injection can be controlled by the bias electric potential. But, generally, depth of the injection is confined to shallow region and thus the energy level control does not have significant meaning.
In the plasma doping of the present invention, because only the germanium source is supplied, the total amount of supply and the concentration of germanium in the gate can be more stably controlled compared to CVD doping method in which the germanium source gas mixed with SiH4 gas is supplied. And, because the germanium source is supplied directly to the process chamber to form germanium plasma and the germanium plasma is directly accelerated to substrate, doping with high dose ranging from 1E16 to 1E17 ions/square centimeter and forming of polycrystalline silicon germanium layer of over 10% germanium concentration can be executed in a practical process.
In the process of making CMOS device, forming of a doping mask pattern which covers the NMOS transistor region before doping germanium plasma makes the plasma doping of germanium be confined within the PMOS transistor region where boron is to be doped.
The plasma doping of germanium is generally made to the surface of the polycrystalline silicon layer revealed. Thus, to prevent gate depletion effectively, it is needed to increase the concentration of germanium of the gate electrode near the gate insulation layer. To increase the concentration of germanium, the polycrystalline silicon layer for gate electrode may be deposited in two or more separated deposition steps and the plasma doping of germanium may be made between the deposition steps.
The present invention also propose a method of forming a CMOS transistor device including the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer only in the region of PMOS transistor.
Generally, forming an element isolation layer is made ahead of forming the gate insulation layer. And, step of patterning the polycrystalline silicon layer to make gate patterns is needed.
To make plasma doping of germanium only to the PMOS transistor region, a step of forming a plasma doping mask covering the NMOS transistor region is needed. Similarly, to dope a type of impurity to source/drain region of N type or P type transistor, steps of forming a impurity doping mask are also needed.